The performance of a microprocessor in data processing applications is affected by its efficiency in communication with system resources. Efficiency includes the cost reduction of a system as a whole, optimization of data transfer time, as well as ability to communicate with a variety of system resources. Although some can, many other memory devices are not capable of accessing subsequent data in a burst. These devices require incremented address inputs pointing to each datum in the burst sequentially. The complexity and cost of interface for these devices is proportional to the size of this interface. System resources include external peripherals and internal modules, neither of which are necessarily of uniform data width ( i.e. port size.) Many times an external device3 s size is a sub-multiple of the bit capability of a microprocessor. This is particularly true when considering 32 bit microprocessors as they may be used to communicate byte (8 bits), word (16 bits), longword (32 bits) or line (128 bits) information to memory that is byte, word, or longword width, all of which are port sizes that are equal to or sub-multiples of the 32 bit microprocessor. To accommodate the potential vagaries of the system, a bus controller, either internally or externally, manages the interface between the central processing unit (CPU) and the various resources of the system. Such a bus controller receives control signals from the CPU as well as the other system resources, and based on these signals determines parameters of data required and configuration of each resource port, and performs requested data transfers. System cost is based on individual costs of each module together with costs of connection devices. These connection devices allow modules to communicate and to function together as a system.
In most system resources which are memories, each unit of data is associated with a unique address. That is, each unique address has associated with it a byte of data. A data transfer involves the processor core supplying an address followed by a read or write of operand data. A memory unit typically requires some device to latch address information received from the system while the device processes the data information associated with that address. In some situations required data length exceeds data port width, for example, the situation in which a processor core requests a word of data while the system's memory device is only capable of byte width sized data transfers. In this case, only the first address or access address is necessary, as successive data is located at subsequent addresses. Some memory devices are capable of supplying subsequent data without being supplied each incremental address. Data is sent in a "burst" starting with the data of the access address and requires no further address information for that particular burst.
Typically, burst data is information to be stored in cache memory for later access. In most cache applications, the length of data to be stored in a cache memory is typically fixed at one line. In most cache applications, the length of total burst and the size of burst increment are each a fixed length, typically line and longword respectively. Burst then is used to efficiently transfer one line of data in four longword size bursts. This proves to be an efficient use of the communication bus or busses and produces a reduction in total cycle count necessary for specific types of data transfers having a fixed burst increment size and a fixed length of data (e.g. one line.) However, these ideas do not fully exploit all concepts of burst transfers and may not reduce system cost as a whole.
There exist many types of system resources, some of which are not capable of accessing the subsequent data in burst transfers (i.e. not burst capable.) These resources typically receive address as an input which is sequentially incremented with each datum in a burst and supplied to the resource externally. The complexity of this external interface to supply address information adversely affects the ease of design, the efficiency, and the cost.